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If your program crashes somewhere outside of WriteProcessMemory call, then this is a bug in your c…
Italo —
So, I made a simple memory scanner that you can see right here: It actually works fine and I'm ve…
sudo459 —
I guess I'm used to "modern" memory protection and being able to directly access hardware and syst…
Jason —
Awesome. Makes total sense. Thanks a lot for the help guys.
I'm pretty sure Casey meant "polling once per frame". Not just "once for key". A mrmixer explained…
Jason —
It was from ep. 13 "Platform-independent user input". You answered my question though and it makes…
If you're talking about an episode precisely give us the number so we can talk about the same thin…
Jason —
Hey all. After going back and looking into some of Casey's initial input handling videos I'm tryin…
@Croepha Thank you! FTMP I think DearImGui is fantastic. To some extent it is held back by decisio…
Could you provide us the code, or a simplified version that has the problem ?
CPU reads from memory in cache line granularity. Regardless whether you are reading uint32 or m128…
yes the lockfile it doing its thing, I just have to toggle the break point off and on again for it…
Draos —
hmmm, i wasn't really conflating bits and bytes, but I guess my post was unclear. what i was tryin…
Nice video, very inspirational. I wasn't aware of LAB colors, now I want to go design to some vis…
I don't think it's safe even for example to change the size of cache lines. The architecture was …
You seem to mix byte and bit together here. m128 is 128bit, which is 16bytes ( two 64bit value, fo…
I am aware you can type only the first n unique chars of a 40-character SHA-1 code when using the …
Forum reply: (Eternal) Screenshot Saturday -- Post images/gifs/videos of your game or other project!
Guntha —
A small game I made last week-end during a "game jam" on the website developpez.com, using a custo…
. It is a finished project in that I did what I wanted to do and don't plan to do any more. It's c…
Draos —
so for example if we had a 32-byte L1 Cache (just for sake of example), if the m128 was aligned to…
There are several layers of caching between the data bus to the ram and the SSE registers. These c…
paked —
So I'm going to start posting any official announcements in here, as well as in the Discord chann…
Draos —
sort of unrelated, but I was wondering why do SIMD m128s need to be aligned to 16-bytes? If the Da…
Yes, they want to use aligned SSE store/load operations. On older CPU's they were significant fast…
Draos —
I did some research and found this statement on Nvidia's site "In order to make copying memory to …
I may be wrong but I think he uploads all the streams, but he doesn't write all the code during th…
Did you try adding a ? In hmh, the problem was that the dll file was written and reloaded before …
Thanks for the reply. I write compilers slightly differently to how Per does it (for example, my …